Memory circuit

A memory circuit comprising a plurality of elementary cells, each comprising:

• a storage cell comprising a first data bit storage node;
• a first read access port comprising a first transistor coupled by its gate to the first storage node, and a second transistor series-assembled with the first transistor between a first node of application of a reference potential of the cell and a first conductive track of the cell;
• and
• a first read and write access port comprising a third transistor coupling the first storage node of the cell to the first conductive track of the cell, the gate of the second transistor being coupled to a second conductive track of the cell and the gate of the third transistor being coupled to a third conductive track of the cell,
• wherein the elementary cells are arranged in a plurality of arrays, each comprising a plurality of rows and a plurality of columns, wherein:
• in each array, the elementary cells of a same row of the array share a same second conductive track and a same third conductive track;
• and
• the elementary cells having the same coordinates in the different arrays share a same first conductive track,
• and wherein the different arrays are respectively formed in a plurality of stacked semiconductor levels of an integrated circuit.