Integrated circuit chip

An integrated circuit chip, comprising:

• a first coupler and a second coupler suitable for coupling data between stacked chips;
• a first transfer circuit suitable for performing a serial-to-parallel conversion onto data of the first coupler and the second coupler to produce a first conversion result and transferring the first conversion result to first to fourth data transfer lines where a portion of the data of the first coupler and the second coupler is inverted and transferred;
• a second transfer circuit suitable for performing a parallel-to-serial conversion onto data of the first to fourth data transfer lines to produce a second conversion result and transferring the second conversion result to fifth and sixth data transfer lines where a portion of the data of the first to fourth data transfer lines is inverted and transferred;
• and
• a third transfer circuit suitable for performing a parallel-to-serial conversion onto data of the fifth and sixth data transfer lines to produce a third conversion result and transferring the third conversion result to a data node.

A memory device, comprising:

• a base die that includes one or more data nodes for transferring and receiving data to and from a host, and one or more couplers that are coupled to one or more transfer lines for coupling data between stacked chips;
• and
• one or more core dies that are stacked over the base die, transfer and receive data to and from the base die through the one or more transfer lines, and include a cell array for storing data,
• wherein the base die includes one or more transfer circuits on a transfer path for transferring data from the one or more couplers to the one or more data nodes, and
• at least one transfer circuit among the one or more transfer circuits inverts a portion of the data which is transferred by the at least one transfer circuit.