Semiconductor memory apparatus
AssigneeSK hynix Inc.
InventorsJoon Woo CHOI, Chang Ki BAEK
Life of this patent
Estimating the term…
Abstract
A semiconductor memory apparatus includes a word line control circuit configured to enable and disable a word line, wherein the word line control circuit comprises a switch which couples and decouples the word line to and from at least one other word line.
Claims22
A semiconductor memory apparatus comprising:
- a word line control circuit configured to enable and disable a first word line,
- wherein the word line control circuit comprises at least one switch that couples and decouples the first word line and a second word line of a set of word lines.
A semiconductor memory apparatus comprising:
- a word line control circuit configured to enable and disable a word line,
- wherein the word line control circuit comprises a switch that couples and decouples the word line and a capacitor.
A semiconductor memory apparatus comprising:
- a first driver configured to enable or disable a first word line in response to a first word line enable signal;
- a first switch configured to couple and decouple the first word line and a second word line in response to a first voltage transfer signal;
- and
- a first control signal generation circuit configured to generate the first voltage transfer signal in response to a refresh signal and the first word line enable signal.
A semiconductor memory apparatus comprising:
- a control signal generation circuit configured to generate a plurality of voltage transfer signals in response to a refresh signal and a word line enable signal;
- and
- a word line control circuit configured to:
- enable or disable a first word line of a set of word lines;
- couple the first word line to a first capacitor of a set of capacitors in response to the plurality of voltage transfer signals;
- and
- decouple the first word line from the first capacitor in response to the plurality of voltage transfer signals.
A method performed by a semiconductor memory apparatus for performing a refresh operation, the method comprising:
- electrically coupling a first word line of the semiconductor memory apparatus to a second word line of the semiconductor memory apparatus;
- transferring charge from the first word line to the second word line;
- and
- activating the second word line after transferring the charge to the second word line.
A semiconductor memory apparatus comprising a word line control circuit configured to:
- electrically couple a second word line of the semiconductor memory apparatus to a first word line of the semiconductor memory apparatus;
- transfer charge from the first word line to the second word line;
- and
- activate the second word line after the transfer of charge to the second word line.
Dependencies are inferred from the claim text.