Management of strobe/clock phase tolerances during extended write preambles

A memory device comprising:

• an input/output interface configured to receive a latency-delayed write signal and a data strobe signal, wherein the input/output interface comprises:
• configuration circuitry configured to receive the latency-delayed write signal and to provide a preamble selection signal, wherein the preamble selection signal indicates a preamble type of a set of preamble types that comprise a first preamble type and a second preamble type;
• a configurable feature detection latch configured to:
• receive the data strobe signal and the preamble selection signal;
• detect a preamble feature in the data strobe signal, wherein the preamble feature is based on the preamble selection signal;
• and
• provide a trigger signal based on the detection of the preamble feature;
• and
• a gating latch configured to receive the data strobe signal and the trigger signal and to provide a gated data strobe signal.

A method to capture data in a memory device from a host, the method comprising:

• receiving a signal associated with a preamble type from the host;
• receiving a data strobe signal on a bidirectional data strobe bus, wherein the data strobe signal comprises a preamble corresponding to the preamble type;
• detecting at least one feature of the preamble based on the preamble type;
• and
• capturing a first bit of the data strobe signal on the bidirectional data strobe bus corresponding to a first edge of the data strobe signal that follows the at least one feature of the preamble.