Ferroelectric memory device and method of programming same

A ferroelectric field effect transistor (FeFET) memory device, comprising:

• a source region and a drain region separated by a channel region;
• a gate structure arranged to interact with the channel region;
• a dielectric structure arranged between the gate structure and the channel region;
• and
• the dielectric structure further at least partly arranged between the gate structure and the source region, and between the gate structure and the drain region,
• wherein the dielectric structure comprises a ferroelectric memory region,
• wherein the gate structure defines a first overlap region with the source region and defines a second overlap region with the drain region, and
• wherein a ratio between a combined area of the first and second overlap regions and an area of an interface between the dielectric structure and the channel region is adapted such that the ferroelectric memory region is programmable by an electric field applied between the gate structure and the source and drain regions through the ferroelectric region.