Shared bit line array architecture for magnetoresistive memory
AssigneeSpin Transfer Technologies, Inc.
InventorsLoc HOANG, Amitay LEVI
Life of this patent
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Abstract
A magnetoresistive memory architecture in one aspect includes a plurality of bit lines each coupled to two or more respective columns of magnetoresistive memory cells, and a plurality of source lines each coupled to a respective one of the columns of memory cells. A given memory cell can be accessed by biasing a selected word line, a selected bit line, and a selected source line coupled to corresponding column of memory cells coupled to the selected bit line, and by counter biasing one or more selected source lines coupled to one or more other columns of memory cells coupled to the selected bit line.
Claims20
A memory device comprising:
- a plurality of memory cells arranged in a plurality of rows and a plurality of columns, wherein each memory cell includes a Magnetic Tunneling Junction (MTJ) and a transistor, wherein a drain of the transistor is coupled to a first terminal of the MJT;
- a plurality of bit lines, wherein each bit line is coupled to a second terminal of the MTJs of the memory cells in two or more respective columns of the memory cells;
- a plurality of source lines;
- wherein each source line is coupled to a source of the transistors of the memory cells in a respective column of the memory cells;
- a plurality of word lines, wherein each word line is coupled to a gate of the transistors of the memory cells in a respective row of the memory cells;
- and
- a control circuit configured to apply corresponding biases to a select word line, a select bit line and a select source line coupled to the select bit line, and to apply a corresponding counter bias to one or more other source lines coupled to the select bit line to write a given value to a given memory cell.
A Magnetoresistive Random-Access Memory (MRAM) comprising:
- a memory cell array including;
- a plurality of magnetoresistive memory cells arranged in a plurality of columns and rows;
- a plurality of word lines, wherein a word line is coupled to a row of the magnetoresistive memory cells;
- a plurality of bit lines, wherein a bit line is coupled to a first and second column of the magnetoresistive memory cells;
- and
- a plurality of source lines, wherein a first source line is coupled to the first column of magnetoresistive memory cells and a second source line is coupled to the second column magnetoresistive memory cells;
- and
- a control circuit coupled to memory cell array, wherein the control circuit is configured to bias the word line, bias the bit lines, bias the first source line and counter bias the second source line to access a given magnetoresistive memory cell.
A method of accessing a Magnetoresistive Random-Access Memory (MRAM) comprising:
- biasing a selected word line coupled to a row of a plurality of Magnetic Tunnel Junction (MTJ) memory cells including a given MTJ memory cell;
- biasing a selected bit line coupled to a first and second column of the plurality of MTJ memory cells, wherein the first column of the plurality of MTJ memory cells includes the given MTJ memory cell;
- biasing a selected source line coupled to the first column of the plurality of MTJ memory cells including the given MTJ memory cell;
- and
- counter biasing a selected source line coupled to the second column of the plurality of MTJ memory cells.
Dependencies are inferred from the claim text.