Apparatuses and methods for duty cycle error correction of clock signals

An apparatus, comprising:

• a duty cycle detector configured to receive a plurality of signals and configured to detect first clock period error between first and second signals and second clock period error between third and fourth signals of the plurality of signals and provide a first control signal indicative of the first clock period error and a second control signal indicative of the second clock period error, the duty cycle detector further configured to detect a duty cycle error relative to the plurality of signals and provide a third control signal indicative of the duty cycle error;
• a duty cycle adjustment circuit configured to receive the first, second, and third control signals from the duty cycle detector and configured to provide adjustment signals based on the first, second, and third control signals;
• and
• a signal driver circuit configured to provide the plurality of signals and to receive the adjustment signals, the signal driver circuit further configured to adjust timings of the plurality of signals based on the first, second, and third control signals.