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US 2019/0198073 A1Published application
Semiconductor device having ranks that performs a termination operation
AssigneeSK hynix Inc.
InventorJae Il KIM
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a first rank and a second rank. The first rank operates in synchronization with a clock signal in response to a first rank selection signal, and the second rank operates in synchronization with the clock signal in response to a second rank selection signal. The first rank performs a termination operation without performing an internal control operation if the first rank selection signal maintains an enabled state in synchronization with a first edge and a second edge of the clock signal.
Claims32
A semiconductor device comprising:
- a first rank configured to operate in synchronization with a clock signal in response to a first rank selection signal;
- and
- a second rank configured to operate in synchronization with the clock signal in response to a second rank selection signal,
- wherein the first rank performs a termination operation by blocking an internal control operation if both a value of the first rank selection sampled by a first edge of the clock signal and a value of the first rank selection sampled by a second edge of the clock signal have an enabled state.
1 more element
A semiconductor device comprising:
- a first rank configured to operate in synchronization with a clock signal in response to a first rank selection signal;
- and
- a second rank configured to operate in synchronization with the clock signal in response to a second rank selection signal,
- wherein the first rank performs a termination operation by blocking an internal control operation if the first rank selection signal is maintained at an enabled state during an interval including a first edge and a second edge of the clock signal, and
- the first edge and the second edge of the clock signal have the same polarity and are created continuously.
2 more elements
A semiconductor device comprising:
- an input circuit configured to receive an clock signal provided by an external device;
- a first rank configured to operate in synchronization with the clock signal in response to a first rank selection signal;
- and
- a second rank configured to operate in synchronization with the clock signal in response to a second rank selection signal,
- wherein the first rank performs a termination operation without performing a memory access operation when the first rank selection signal is maintained at an enabled state during two cycles of the clock signal.
2 more elements
A semiconductor device comprising:
- a first rank configured to operate in synchronization with an external clock signal in response to a first rank selection signal;
- and
- a second rank configured to operate in synchronization with the external clock signal in response to a second rank selection signal,
- wherein the first rank performs a termination operation by blocking an internal control operation if a value of the first rank selection sampled by a first edge of the external clock signal is the same with a value of the first rank selection sampled by a second edge of the external clock signal, and
- the first edge and the second edge of the external clock signal have the same polarity and are created continuously.
2 more elements
A semiconductor device comprising:
- a first rank configured to operate in synchronization with a clock signal in response to a first rank selection signal;
- and
- a second rank configured to operate in synchronization with the clock signal in response to a second rank selection signal,
- wherein the first rank performs a termination operation when the first rank selection signal is maintained at an enabled state during an interval of a first edge and a second edge of the clock signal,
- the first rank performs an internal control operation when the first rank selection signal has the enabled state at the first edge of the clock signal and has a disabled state at the second edge of the clock signal, and
- the first edge and the second edge of the clock signal have a same polarity and are created continuously.
3 more elements
A semiconductor device comprising:
- an input circuit configured to receive an clock signal provided by an external device;
- a first rank configured to operate in synchronization with the clock signal in response to a first rank selection signal;
- and
- a second rank configured to operate in synchronization with the clock signal in response to a second rank selection signal,
- wherein the first rank performs a termination operation by blocking a memory access operation when the first rank selection signal is maintained at an enabled state during two cycles of the clock signal.
2 more elements
A semiconductor device comprising:
- a first rank configured to operate in synchronization with a clock signal in response to a first rank selection signal;
- and
- a second rank configured to operate in synchronization with the clock signal in response to a second rank selection signal,
- wherein the first rank performs a termination operation by blocking a memory access operation if both a value of the first rank selection sampled by a first edge of the clock signal and a value of the first rank selection sampled by a second edge of the clock signal have an enabled state.
1 more element
Dependencies are inferred from the claim text.