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US 2019/0198072 A1Published application
Clock monitoring circuit
AssigneeSK hynix Inc.
InventorsMyeong-Jae PARK, Young-Jae CHOI
Life of this patent
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Abstract
A clock monitoring circuit includes: a sampling circuit suitable for sampling a monitoring target clock in synchronization with a sampling clock; a first counter circuit suitable for counting the number of times that the sampling circuit samples the monitoring target clock at a predetermined level; and a second counter circuit suitable for counting the number of times that the sampling circuit performs sampling.
Claims19
A clock monitoring circuit, comprising:
- a sampling circuit suitable for sampling a monitoring target clock in synchronization with a sampling clock;
- a first counter circuit suitable for counting the number of times that the sampling circuit samples the monitoring target clock at a predetermined level;
- and
- a second counter circuit suitable for counting the number of times that the sampling circuit performs sampling.
1 more element
A clock monitoring circuit, comprising:
- a sampling circuit suitable for sampling a monitoring target clock in synchronization with a sampling clock;
- a first counter circuit suitable for counting the number of times that the sampling circuit samples the monitoring target clock at a predetermined level;
- a second counter circuit suitable for counting the number of times that the sampling circuit performs sampling;
- and
- an output circuit suitable for outputting a counting result of the first counter circuit and a counting result of the second counter circuit.
2 more elements
Dependencies are inferred from the claim text.