Memory device for performing internal process and operating method thereof

A memory device comprising:

• a buffer die including an internal command generator configured to serially generate internal commands so that an internal process corresponding to a command received from the outside is performed;
• a first through N core dies including separate channels configured to communicate in accordance with independent interfaces (N is integer greater than 1), each of the first through N core dies including a processor in memory (PIM) performing a processing operation with respect to data;
• and
• an internal common bus disposed to be shared by the channels and configured to form a transmission path of data between the channels when the internal process is performed,
• wherein the internal process includes an RMW (Read Modify Write) operation for writing write data in a cell core of the first core die in an RMW method, and
• wherein the first core die includes a first PIM configured to perform calculation processing for the write data and read data read from the cell core of the first core die.

A memory device comprising:

• a buffer die including an internal command generator configured to serially generate internal commands so that an internal process corresponding to a command received from the outside is performed;
• a first through N core dies including separate channels configured to communicate in accordance with independent interfaces (N is integer greater than 1), each of the first through N core dies including a processor in memory (PIM) performing a processing operation with respect to data;
• and
• an internal common bus disposed to be shared by the channels and configured to form a transmission path of data between the channels when the internal process is performed,
• wherein the internal process includes a mask write operation in which data is mask-written in a first cell core of the first core die,
• wherein the first core die includes a first PIM and the second core die includes a second PIM, and
• wherein each of the first PIM and the second PIM controls data to be provided to the first cell core based on a bit value of mask data.