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US 2019/0197945 A1Published application
Source signal driving apparatus for display device
AssigneeSilicon Works Co., Ltd.
InventorYoung Gi KIM
Life of this patent
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Abstract
Disclosed is a source signal driving apparatus capable of implementing channels at high integration density. The source signal driving apparatus is configured to sequentially output source signals by sequentially delaying enable time points of enable signals provided to channel circuits.
Claims18
A source signal driving apparatus for a display device, comprising:
- a plurality of channel circuits formed in one driver implemented as a chip, divided into a plurality of groups, and each configured to output source signals;
- a controller configured to provide one or more enable signals;
- and
- transfer buffers each configured to transfer the one or more enable signals between a pair of groups, delay enable time points of the one or more enable signals by a preset time, and transfer the one or more enable signals,
- wherein the one or more enable signals are sequentially transferred to the plurality of groups while the enable time points are gradually delayed by the transfer buffers, and
- the plurality of channel circuits sequentially output the source signals at different enable time points by the one or more enable signals for the respective groups.
3 more elements
A source signal driving apparatus for a display device, comprising:
- a plurality of channel circuits formed in one driver implemented as a chip, divided into a plurality of groups, and each configured to output source signals;
- and
- a controller configured to provide the groups with an equal number of one or more enable signals having different enable time points for the respective groups,
- wherein the plurality of channel circuits sequentially output the source signals at different enable time points by the one or more enable signals for the respective groups.
1 more element
A source signal driving apparatus for a display, comprising:
- a plurality of channel circuits formed in one driver implemented as a chip, divided into a plurality of groups, and each configured to output source signals;
- a controller configured to provide enable data which is enabled during an enable period for outputting the source signals and a shift clock which has a plurality of cycles during the enable period;
- and
- signal providing units corresponding to the respective groups, and each configured to provide one or more enable signals to the corresponding group,
- wherein the enable data and the shift clock are sequentially transferred to the enable signal providing units,
- the enable signal providing units generate the one or more enable signals having enable time points which are sequentially delayed in synchronization with the shift clock according to the transfer order of the enable data and the shift clock, and
- the plurality of channel circuits sequentially output the source signals in response to different enable time points by the one or more enable signals for the respective groups.
4 more elements
Dependencies are inferred from the claim text.