Processor, information processing apparatus, and operation method of processor
AssigneeFujitsu Limited
InventorsKatsuhiro Yoda, Mitsuru Tomono, Takahiro Notsu
Life of this patent
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AssigneeFujitsu Limited
InventorsKatsuhiro Yoda, Mitsuru Tomono, Takahiro Notsu
Estimating the term…
A processor includes; a first memory configured to store image data including pixel data of a plurality of pixels that are two-dimensionally arranged; a second memory configured to store neighborhood matrix image data including pixel data of a neighborhood matrix; and a format converter that includes (a) a readout circuit configured to read out the image data from the first memory, (b) a padding arithmetic unit configured to receive the read-out image data, select pixel data of the received read-out image data and padding data inserted at periphery of the plurality of pixels in accordance with mask values of a padding mask, and generate the neighborhood matrix image data including the pixel data and the padding data, and (c) a writing circuit configured to write the neighborhood matrix image data to the second memory.
A processor comprising:
An information processing apparatus comprising:
An operation method performed by a processor including a first memory, a second memory, and a format converter, the first memory being configured to store image data including pixel data of a plurality of pixels that are two-dimensionally arranged, the second memory being configured to store neighborhood matrix image data including pixel data of a neighborhood matrix, the format converter being configured to generate the neighborhood matrix image data, the operation method comprising:
Dependencies are inferred from the claim text.