Integrated circuit including load standard cell and method of designing the same
AssigneeSamsung Electronics Co., Ltd.
InventorsKwan-Yeob Chae, Jong-Ryun Choi
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Abstract
To design an integrated circuit, input data defining an integrated circuit are received, and a plurality of load standard cells having different delay characteristics are provided in a standard cell library. Placement and routing are performed based on the input data and the standard cell library and output data defining the integrated circuit are generated based on a result of the placement and the routing. Design efficiency and performance of the integrated circuit are enhanced by designing the integrated circuit with delay matching and duty ratio adjustment using the load standard cell.
Claims20
A method of designing an integrated circuit, comprising:
- receiving input data defining an integrated circuit;
- providing, in a standard cell library, a plurality of load standard cells having different delay characteristics;
- performing placement and routing based on the input data and the standard cell library;
- and
- generating output data defining the integrated circuit based on a result of the placement and the routing.
An integrated circuit comprising:
- a logic standard cell including a delay node requiring a delay;
- and
- a load standard cell including a load node that connected to the delay node, the load standard cell configured to provide the required delay.
An integrated circuit comprising:
- a first logic standard cell including a first delay node;
- a second logic standard cell including a second delay node;
- a first load standard cell including a first load node providing a first delay, the first load node connected to the first delay node;
- and
- a second load standard cell including a second load node providing a second delay different from the first delay, the second load node connected to the second delay node.
Dependencies are inferred from the claim text.