Systolic array of pipelined processing engines for implementing dynamic programming algorithms

A method of operating an integrated circuit, comprising:

• with a first memory circuit, storing a first sequence;
• with a second memory circuit, storing a second sequence;
• and
• with systolic array circuitry, receiving the first and second sequences and aligning the first and second sequences by computing a substitution matrix, dividing the substitution matrix into multiple segments, and computing scores for the multiple segments in parallel.

An integrated circuit, comprising:

• a first memory storing a first sequence;
• a second memory storing a second sequence;
• and
• a systolic array that aligns the first and second sequences, wherein the systolic array comprises:
• a first processing engine having an input;
• a second processing engine having an output;
• and
• a multiplexer that selectively feeds data from the output of the second processing engine to the input of the first processing engine.