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US 2019/0197015 A1Published application
Parallel memory systems
AssigneeHyperion Core, Inc.
InventorMartin Vorbach
Life of this patent
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Abstract
The invention relates to a multi-core processor memory system, wherein it is provided that the system comprises memory channels between the multi-core processor and the system memory, and that the system comprises at least as many memory channels as processor cores, each memory channel being dedicated to a processor core, and that the memory system relates at run-time dynamically memory blocks dedicatedly to the accessing core, the accessing core having dedicated access to the memory bank via the memory channel.
Claims8
A memory device comprising:
- a plurality of memory banks, each memory bank associated with a memory bank controller controlling the memory bank;
- and
- a plurality of data transmission channels,
- each of the memory bank controllers and each of the plurality of data transmission channels being connected to a switch for flexible interconnecting of the plurality of data transmission channels and the memory bank controllers.
1 more element
Dependencies are inferred from the claim text.