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US 2019/0197008 A1Published application
Pcie switch with data and control path systolic array
AssigneeExten Technologies, Inc.
InventorsHarish Kumar Shakamuri, Ashwin Kamath, Michael Enz
Life of this patent
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Abstract
The present subject disclosure provides a switch architecture with data and control path systolic array that can be used for real time data analysis or Artificial Intelligence (AI) learning. A systolic array is described which analyzes the TLPs received by an uplink port and processes the TLPs according to pre-programmed rules. Then the TLP is forwarded to a destination port. The reverse operation is described as well.
Claims14
A method for switching, comprising:
- receiving a transaction layer packet (TLP) at an uplink port of a switch;
- at the switch:
- determining a nature of the TLP by evaluating a parameter of the TLP at a filter coupled to the uplink port;
- determining if the TLP should be routed to a systolic array at the switch based on the nature of the TLP determined by the filter;
- routing the TLP to the systolic array at the switch based on a determination that the TLP should be routed to the systolic array at the switch;
- analyzing, at the switch, the TLP in the systolic array;
- and
- forwarding the TLP to a destination port of the switch based on the analysis of the TLP performed by the systolic array of the switch.
5 more elements
A switch, comprising:
- an uplink port for receiving a transaction layer packet (TLP) at the switch;
- a filter coupled to the uplink port, the filter for determining a nature of the TLP received at the uplink port by evaluating a parameter of the received TLP, determining if the TLP should be routed to a systolic array at the switch based on the nature of the TLP determined by the e filter and routing the TLP to the systolic array at the switch based on a determination that the TLP should be routed to the systolic array at the switch;
- the systolic array for analyzing the TLP at the switch and forwarding the TLP to a destination port of the switch based on the analysis of the TLP performed by the systolic array of the switch;
- and
- a destination port for receiving the TLP.
2 more elements
Dependencies are inferred from the claim text.