Dual i2c and spi slave for fpga and asic implementation
AssigneeUnited States of America as represented by the Administrator of NASA
InventorsGeorge Suarez, Jeffrey J. Dumonthier, George E. Winkert
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Abstract
A digital serial communication system includes a first serial communication circuit configured to exchange information utilizing a first communication protocol, a second serial communication circuit configured to exchange information utilizing a second communication protocol, and a common bus interface configured to couple the first serial communication circuit to a first serial communication bus implementing the first communication protocol, and configured to couple the second serial communication circuit to a second serial communication bus implementing the second communication protocol.
Claims18
A digital serial communication system comprising:
- a first serial communication circuit configured to exchange information utilizing a first communication protocol;
- a second serial communication circuit configured to exchange information utilizing a second communication protocol;
- a common bus interface configured to couple the first serial communication circuit to a first serial communication bus implementing the first communication protocol, and configured to couple the second serial communication circuit to a second serial communication bus implementing the second communication protocol;
- wherein the common bus interface comprises a signal line having a first state for enabling the first selectable serial communication circuit and disabling the second selectable serial communication circuit, and a second state for disabling the first selectable serial communication circuit and enabling the second selectable serial communication circuit;
- further comprising a register bank connected to the first and second serial communication circuits and configured to store data from the first and second serial communication circuits;
- a multiplexer coupled between the first and second serial communication circuits and the register bank;
- a third signal path between the first serial communication circuit and the multiplexer;
- and
- a fourth signal path between the second serial communication circuit and the multiplexer
- wherein the multiplexer including an input connected to the common bus interlace signal line and wherein the multiplexer is configured to connect the third signal path to the register bank when the common bus interface signal is in the first state, and to connect the fourth signal path to the register bank when the common bus interface signal is in the second state;
- wherein the register bank comprises
- a read/write register;
- a read only register;
- and
- decoder circuitry that, upon receiving a specially designated address to which data is to be written, transfers data from the read/write register to the read only register.
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A digital serial communication method, comprising:
- using a common bus interface to selectively:
- couple a first serial communication circuit to a first serial communication bus implementing a first communication protocol;
- and
- couple a second serial communication circuit to a second serial communication bus implementing a second communication protocol;
- exchanging information through one of the first and second serial communication circuit utilizing one of the first communication protocol and the second communication protocol, respectively;
- storing data from the first and second serial communication circuits in a read/write register of a register bank;
- and
- transferring data from the read/write register to a read only register of the register bank upon receiving a specially designated address to which data is to be written.
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Dependencies are inferred from the claim text.