Scaling interface architecture between memory and programmable logic
AssigneeIntel Corporation
InventorChee Hak Teh
Life of this patent
Estimating the term…
Abstract
Systems and methods for an interface with a widened interface-to-fabric shoreline between semiconductor circuits and a narrower interface-to-memory controller shoreline. The interface providing transitions from a first clock of a first circuit (e.g., field-programmable gate array (FPGA)), a second clock of a second circuit (e.g., high-bandwidth memory generation 2 (HBM2) stack, and a third clock of a physical layer of the second circuit. A first transfer between the first clock and the second clock may use a first set of first-in first-outs (FIFO) buffers, such as rate-matching FIFO buffers. A second transfer between the second clock and the third clock may use a second set of FIFO buffers, such as phase compensation FIFOs.
Claims20
A device package comprising:
- a programmable logic circuit operating in a first clock domain driven by a first clock;
- a memory controller operating in a second clock domain driven by a second clock, wherein a speed of the first clock is less than or equal to a speed of the second clock;
- and
- an interface between the programmable logic circuit that provides transfers between the programmable logic circuit in the first clock domain and the memory controller in the second clock domain, wherein the interface comprises:
- a programmable logic circuit edge that couples to the programmable logic circuit and extends a width of the programmable logic circuit;
- and
- a memory controller edge that couples to the memory controller and is narrower than the programmable logic circuit edge to provide equidistant routing on interconnects in the interface.
An integrated circuit device package, comprising:
- a programmable logic circuit;
- an interface comprising a plurality of channels each comprising a plurality of rate-matching first-in first-outs (FIFO) buffers, wherein the interface couples the programmable logic circuit to another circuit, wherein the interface:
- communicates with the programmable logic fabric using a first clock domain;
- uses another circuit controller that controls the other circuit, wherein the other circuit controller uses a second clock domain;
- and
- communicates with a physical layer, wherein each rate-matching FIFO buffer of the plurality of rate-matching FIFO buffers transfers from the first clock domain to the second clock domain or from the second clock domain to the first clock domain for a corresponding channel of the plurality of channels.
A memory interface apparatus comprising:
- a programmable logic core interface that interfaces with a programmable logic core using a first clock;
- a high-bandwidth memory generation 2 (HBM2) interface that interfaces with an HBM2 stack using a second clock;
- a rate-matching first-in first-out (FIFO) buffer that transfers between a first clock domain of the programmable logic core driven by the first clock and a second clock domain of the HBM2 stack driven by the second clock;
- a physical layer interface that interfaces with a physical layer using a third clock;
- and
- a phase compensation FIFO buffer that transfers between the second clock domain and a third clock domain of the physical layer driven by the third clock.
Dependencies are inferred from the claim text.