Semiconductor device and bus generator
AssigneeRenesas Electronics Corporation
InventorsSho YAMANAKA, Toshiyuki HIRAKI, Nobuhiko HONDA
Life of this patent
Estimating the term…
Abstract
Each master issues an access request including a read request and a write request to a memory. A cache caches the write request issued by the master. A central bus control system performs access control for the read request issued by each master and the write request output by the cache. A central bus control system performs access control for the write request issued by each master. The central bus control system performs access control in accordance with a free situation of a buffer of a memory controller. The central bus control system performs access control in accordance with a free situation of the cache.
Claims20
A semiconductor device comprising:
- a master which issues access requests including a read request and a write request to a memory;
- a memory controller which is coupled to the master through a bus, and accesses the memory in accordance with the access request;
- a cache which is arranged between the memory controller and the master, and, when the access request is a write request, caches this write request;
- a first access control unit which performs first access control for controlling output for the read request issued by the master to the memory controller and output for the write request cached in the cache to the memory controller;
- and
- a second access control unit which performs second access control for controlling output for the write request issued by the master to the memory controller,
- wherein the second access control unit performs the second access control in accordance with a free situation of the cache.
A bus generator which generates a bus in a semiconductor device, comprising:
- a bus structure information generation unit which generates, based on information regarding a master outputting access requests including a read request and a write request to the memory and information regarding a slave accessed from the master, structure information of a bus for coupling between the master and the slave;
- a central bus control unit generation unit which generates circuit information of a central bus control system performing access control for a read request output by the master, write-back of the cache, and a write request output by the master, using the structure information of the bus, information regarding a cache temporarily storing the write request and performing the write-back, service quality information of the master, and circuit information of functional blocks;
- a sub-bus control unit generation unit which generates circuit information of a sub-bus control system operating under control of the central bus control system, using the circuit information of the central bus control system;
- a bus part generation unit which generates circuit information of a bus part, using the structure information of the bus and the circuit information of the functional blocks;
- and
- a merge unit which merges the circuit information of the central bus control system, the circuit information of the sub-bus control system, and the circuit information of the bus part, and generates circuit information of the bus.
Dependencies are inferred from the claim text.