Dynamically determining memory access burst length
AssigneeAdvanced Micro Devices, Inc.
InventorsKedarnath Balakrishnan, Ravindra N. Bhargava, Guanhao Shen, James Raymond Magro, Kevin M. Brandl
Life of this patent
Estimating the term…
Loading patent…
AssigneeAdvanced Micro Devices, Inc.
InventorsKedarnath Balakrishnan, Ravindra N. Bhargava, Guanhao Shen, James Raymond Magro, Kevin M. Brandl
Estimating the term…
Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. When a memory controller in a computing system determines a threshold number of memory read requests have been sent to a memory device in a read mode of a data bus, the memory controller determines a threshold number of memory write requests to send to the memory device in an upcoming write mode is a number of outstanding memory write requests. Alternatively, the memory controller determines the threshold number of memory write requests to send to the memory device in an upcoming write mode is a maximum value of the number of outstanding memory write requests and a programmable value of the write burst length stored in a control register. Therefore, the write burst length is determined dynamically. Similarly, the read burst length is determined dynamically when the write mode ends.
A memory controller comprising:
A method, comprising:
A computing system comprising:
Dependencies are inferred from the claim text.