Dynamic page state aware scheduling of read/write burst transactions
AssigneeAdvanced Micro Devices, Inc.
InventorsGuanhao Shen, Ravindra N. Bhargava, Kedarnath Balakrishnan
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AssigneeAdvanced Micro Devices, Inc.
InventorsGuanhao Shen, Ravindra N. Bhargava, Kedarnath Balakrishnan
Estimating the term…
Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. When a memory controller in a computing system determines a threshold number of memory access requests have not been sent to the memory device in a current mode of a read mode and a write mode, a first cost corresponding to a latency associated with sending remaining requests in either the read queue or the write queue associated with the current mode is determined. If the first cost exceeds the cost of a data bus turnaround, the cost of a data bus turnaround comprising a latency incurred when switching a transmission direction of the data bus from one direction to an opposite direction, then a second cost is determined for sending remaining memory access requests to the memory device. If the second cost does not exceed the cost of the data bus turnaround, then a time for the data bus turnaround is indicated and the current mode of the memory controller is changed.
A memory controller comprising:
A method, comprising:
A computing system comprising:
Dependencies are inferred from the claim text.