Partial link width states for multilane links
AssigneeIntel Corporation
InventorDebendra Das Sharma
Life of this patent
Estimating the term…
Abstract
Systems and devices can include an upstream port, a downstream port, and a multilane link connecting the upstream port to the downstream port, the multilane link comprising a first link width. The upstream port or the downstream port can be configured to determine that the downstream port is to operate using a second link width, the second link width less than the first link width; transmit to the upstream port an indication of a last data block for the first link width across one or more lanes of the multilane link; cause a first set lanes to enter an idle state; and transmit data on a second set of lanes, the second set of lanes defining the second link width.
Claims34
An apparatus comprising:
- a port;
- and
- a multilane link coupled to the port, the multilane link operating at a first link width;
- the port comprising hardware circuitry to:
- determine that the port is to operate using a second link width, the second link width less than the first link width;
- transmit an indication of a last data block for the first link width across one or more lanes of the multilane link;
- cause a first set lanes to enter an idle state;
- and
- transmit data on a second set of lanes, the second set of lanes defining the second link width.
A method performed by a port coupled to a multilane link, the multilane link comprising a first link width, the method comprising:
- determining that a port of a multilane link is to operate using a second link width, the second link width less than the first link width;
- transmitting an indication of a last data block for the first link width across one or more lanes of the multilane link;
- causing a first set lanes to enter an idle state;
- and
- transmitting data on a second set of lanes, the second set of lanes defining the second link width.
A non-transitory computer-readable medium having program instructions stored therein, wherein the program instructions are executable by a computer system to perform operations comprising:
- determining that the port is to operate using a second link width, the second link width less than the first link width;
- transmitting an indication of a last data block for the first link width across one or more lanes of the multilane link;
- causing a first set lanes to enter an idle state;
- and
- transmitting data on a second set of lanes, the second set of lanes defining the second link width.
A system comprising:
- an upstream port;
- a downstream port;
- and
- a multilane link connecting the upstream port to the downstream port, the multilane link comprising a first link width;
- the downstream port to:
- determine that the downstream port is to operate using a second link width, the second link width less than the first link width;
- transmit to the upstream port an indication of a last data block for the first link width across one or more lanes of the multilane link;
- cause a first set lanes to enter an idle state;
- and
- transmit data on a second set of lanes, the second set of lanes defining the second link width.
Dependencies are inferred from the claim text.