Method, system, and apparatus for reducing processor latency
AssigneeInternational Business Machines Corporation
InventorShakti Kapoor
Life of this patent
Estimating the term…
Abstract
Disclosed is a method, apparatus, and/or computer program product for reducing latency in a processor with regard to the execution of noncacheable operations that includes receiving noncacheable operations from one or both of the level 2 cache and a level 3 cache, sending the noncacheable operations to a noncacheable unit (NCU) associated with a core of the processor, executing the noncacheable operations by the NCU, and sending results of the executed noncacheable operations to a host bridge for output to an input/out device. The noncacheable operations bypass the core of the processor.
Claims20
A method executed in a coherent engine for reducing latency in a processor, the method comprising:
- receiving a source location, a data size, and a destination location;
- retrieving data from the source location;
- sending the data to a noncacheable unit (NCU) associated with a core of the processor to be output and bypassing the core resulting in reduced latency.
A system for reducing latency in a processor, the system comprising:
- a non-cacheable unit (“NCU”) configured to perform non-cacheable operations, wherein the NCU is associated with a core of a processor;
- and
- a coherent engine configured to retrieve data from a source memory location and store it at a destination location bypassing the core resulting in reduced latency.
A computer readable medium comprising program code that, when executed, causes a coherent engine to execute a method for reducing latency in a processor, wherein the method comprises:
- receiving a source location, a data size, and a destination location;
- retrieving data from the source location;
- sending the data to a noncacheable unit (NCU) associated with a core of the processor to be output and bypassing the core resulting in reduced latency.
Dependencies are inferred from the claim text.