Method, apparatus, and system for dynamic management of integrity-protected memory
AssigneeQUALCOMM Incorporated
InventorsDarren LASKO, Roberto Avanzi
Life of this patent
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AssigneeQUALCOMM Incorporated
InventorsDarren LASKO, Roberto Avanzi
Estimating the term…
In certain aspects of the disclosure, an apparatus, comprises a first memory having a plurality of bits. Each bit of the plurality of bits of the first memory is associated with a region of a second memory, and each bit indicates whether the associated region of the second memory is to be integrity-protected. The first memory further stores a first minimum set of data necessary for integrity protection (MSD) of an associated first integrity protection tree when a first bit of the plurality of bits is set to a value indicating that the first associated region of the second memory is to be integrity-protected. Regions of the second memory that are integrity-protected may be non-contiguous, and may be adjusted during run-time.
An apparatus, comprising:
A method, comprising:
An apparatus, comprising:
A non-transitory computer readable medium comprising instructions which, when executed by a processor, cause the processor to:
Dependencies are inferred from the claim text.