Unblock instruction to reverse page block during paging

A system comprising:

• a plurality of processor cores, each comprising a translation lookaside buffer (TLB);
• a secure enclave circuit comprising a secure storage structure to store an enclave page cache map, wherein the enclave page cache map is to track contents of a secure enclave within system memory, the secure enclave to store secure data comprising a page having a virtual address;
• and
• an execution unit operatively coupled to the secure enclave circuit and the plurality of processor cores, wherein the execution unit is to, in response to a request to evict the page from the secure enclave, execute a plurality of decoded instructions to:
• block creation of translations of the virtual address;
• record one or more hardware threads currently accessing the secure data in the secure enclave;
• send an inter-processor interrupt to one or more of the plurality of processor cores associated with the one or more hardware threads, to cause the one or more hardware threads to exit the secure enclave and to flush the TLB of the one or more of the plurality of processor cores;
• and
• in response to detection of a page fault associated with the virtual address for the page in the secure enclave, unblock creation of further translations of the virtual address.

A method comprising:

• storing, in a secure enclave of main memory of a computing system, secure data comprising a page having a virtual address;
• storing, in a secure storage structure of a secure enclave circuit of the computing system, an enclave page cache map to track contents of the secure enclave within the system memory;
• and
• in response to a request to evict the page from the secure enclave:
• blocking creation of translations of the virtual address;
• recording one or more hardware threads currently accessing the secure data in the secure enclave;
• sending an inter-processor interrupt to one or more cores associated with the one or more hardware threads, to cause the one or more hardware threads to exit the secure enclave and to flush translation lookaside buffers of the one or more cores;
• and
• in response to detecting a page fault associated with the virtual address for the page in the secure enclave, unblocking creation of translations of the virtual address.

A processor comprising:

• a secure enclave circuit comprising a secure storage structure to store an enclave page cache map (EPCM), wherein the EPCM is to track contents of a secure enclave within system memory, the secure enclave to store secure data comprising a page at a virtual address, and wherein the EPCM is to store a first blocked bit to indicate whether the page is blocked;
• and
• a processor core operatively coupled to the secure enclave circuit, the processor core to execute a virtual machine monitor (VMM) to manage paging within the secure enclave for a virtual machine (VM), wherein to evict the page from the secure enclave, the VMM is to:
• set the first blocked bit in the EPCM to indicate the page is blocked from further translation of the virtual address for access to the page;
• generate a block state bit, indicative of a state of the first blocked bit, to set a second blocked bit within a first field of an information data structure stored in the system memory;
• execute a write-back instruction to copy a value of the second blocked bit into a blocked bit flag of a unified metadata structure (UMDS), wherein the UMDS is to be stored in a version array page of the secure enclave;
• and
• remove the page from the secure enclave to one of the system memory, outside of the secure enclave, or to disk.