Single instruction multiple data page table walk scheduling at input output memory management unit
AssigneeAdvanced Micro Devices, Inc.
InventorsArkaprava Basu, Eric Van Tassell, Mark Oskin, Guilherme Cox, Gabriel Loh
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Abstract
A data processing system includes a memory and an input output memory management unit that is connected to the memory. The input output memory management unit is adapted to receive batches of address translation requests. The input output memory management unit has instructions that identify, from among the batches of address translation requests, a later batch having a lower number of memory access requests than an earlier batch, and selectively schedules access to a page table walker for each address translation request of a batch.
Claims20
An input output memory management unit (IOMMU), comprising:
- a page table scheduler for:
- receiving page table walk requests for an address translation for memory accesses;
- and
- reordering the page table walk requests such that an order of dispatching the page table walk requests is based on a priority determination, wherein the page table walk requests are from a batch of memory requests that are generated in response to execution of a same single instruction multiple data (SIMD) instruction;
- and
- a page table walker for receiving, from the page table scheduler, the page table walk requests and walking page tables associated with the page table walk requests in response to the ordering.
A data processing system, comprising:
- a memory;
- an input output memory management unit coupled to the memory and adapted to receive batches of address translation requests, wherein the input output memory management unit has instructions that:
- identifies, from among the batches of address translation requests, a later batch having a lower number of memory access requests than an earlier batch;
- and
- selectively schedules access to a page table walker for each address translation request of an identified batch.
A method for scheduling address translations for a batch of address translation requests, comprising:
- receiving a page table walk request for the batch of address translation requests at an input output memory management unit, wherein the batch of address translation requests is a selection of address translation requests generated by execution of a same single instruction multiple data (SIMD) instruction;
- identifying a SIMD instruction identification that is associated with the batch of address translation requests;
- determining a total number of memory accesses needed to service the batch of address translation requests;
- totaling the total number of memory accesses per batch of address translation requests to formulate a page table lookup count for each batch;
- and
- in response to the totaling, dispatching a later batch of address translation requests having a lower number of page table accesses than an earlier batch of address translation requests.
Dependencies are inferred from the claim text.