Tag accelerator for low latency dram cache

A method comprising:

• detecting a match to a first tag in a first row of a data cache for a first address of a first memory request;
• retrieving a plurality of tags which are adjacent to the first tag in the first row of the data cache, wherein the plurality of tags comprise at least a second tag;
• storing the plurality of tags and corresponding data addresses in a tag accelerator cache;
• retrieving, from the tag accelerator cache, a data address corresponding to the second tag responsive to detecting a match to the second tag for a second address of a second memory request;
• and
• accessing a cache line, within the first row of the data cache, at a column corresponding to the data address of the second tag without having performed a tag lookup of the data cache for the second memory request.

An apparatus comprising:

• a data cache;
• a memory controller;
• a tag accelerator cache;
• and
• a coherent slave unit coupled to the data cache via the memory controller, wherein the coherent slave unit is configured to:
• detect a match to a first tag in a first row of the data cache for a first address of a first memory request;
• retrieve a plurality of tags which are adjacent to the first tag in the first row of the data cache, wherein the plurality of tags comprise at least a second tag;
• store the plurality of tags and corresponding data addresses in the tag accelerator cache;
• retrieve, from the tag accelerator cache, a data address corresponding to the second tag responsive to detecting a match to the second tag for a second address of a second memory request;
• and
• access a cache line, within the first row of the data cache, at a column corresponding to the data address of the second tag without having performed a tag lookup of the data cache for the second memory request.