US 2019/0196973 A1 · MEMORY CIRCUIT WITH ANALOG BYPASS PORTION

Abstract

One example includes a memory circuit. The circuit includes a memory array arranged as rows and columns of memory cells. An array portion stores a respective memory word in a given one of the rows in response to a word-write signal corresponding to a write address of the given one of the rows and in response to a plurality of bit-write signals associated with the plurality of columns, and reads a respective memory word from a given one of the rows in response to a word-read signal corresponding to a read address of the given one of the rows and in response to a plurality of bit-read signals associated with the plurality of columns. The circuit also includes a write-through detection system that activates an analog bypass portion to read the memory word from the analog bypass portion in response to the read address being equal to the write address.

Claims20

Dependent claims

A memory circuit comprising:

a memory array comprising an array portion and an analog bypass portion, the array portion comprising rows and columns of memory cells, the array portion stores a respective memory word in a given one of the rows in response to a word-write signal corresponding to a write address of the given one of the rows and in response to a plurality of bit-write signals associated with the plurality of columns, and to read a respective memory word from a given one of the rows in response to a word-read signal corresponding to a read address of the given one of the rows and in response to a plurality of bit-read signals associated with the plurality of columns;
and
a write-through detection system that activates the analog bypass portion to read the memory word from the analog bypass portion in response to the read address being equal to the write address.

A method for reading data from a memory array during a write operation, the memory array comprising rows and columns of memory cells, the method comprising:

providing a write address signal corresponding to a write address of the given one of the rows;
providing a word-write signal associated with the write address via a write address decoder to activate the respective one of the rows during a write operation;
providing a plurality of bit-write signals associated with the respective columns of the memory array to store a memory word in the respective one of the rows during the write operation;
providing a read address signal corresponding to a read address of a respective one of the rows during the write operation;
comparing the read address signal and the write address signal;
activating an analog bypass portion of the memory array in response to the read address signal being equal to the write address signal;
and
reading the memory word from the analog bypass portion of the memory array in response to activation of the analog bypass portion.

5 more elements

A memory circuit comprising:

a memory array comprising an array portion and an analog bypass portion, the array portion comprising rows and columns of memory cells, each of the memory cells comprising a superconducting hysteretic memory element and each of a plurality of cells of the analog bypass portion comprising a superconducting read element, the array portion storing a respective memory word in a given one of the rows in response to a word-write signal corresponding to a write address of the given one of the rows and in response to a plurality of bit-write signals associated with the plurality of columns, and to read a respective memory word from a given one of the rows in response to a word-read signal corresponding to a read address of the given one of the rows and in response to a plurality of bit-read signals associated with the plurality of columns;
and
a write-through detection system that activates the analog bypass portion to read the plurality of bit-write signals corresponding to the memory word from the analog bypass portion in response to the read address being equal to the write address.

Dependencies are inferred from the claim text.

Memory circuit with analog bypass portion

Life of this patent

Memory circuit with analog bypass portion

Life of this patent

Abstract

Claims20