Memory system and operating method thereof
AssigneeSK hynix Inc.
InventorsSeung Gu JI, Chung Un NA, Byeong Gyu PARK
Life of this patent
Estimating the term…
Abstract
A memory system includes a plurality of memory devices, each including a plurality of memory blocks; and a controller configured to evaluate performance grades of the plurality of memory blocks, form super blocks spanning the plurality of memory devices by selecting memory blocks, among the plurality of memory blocks, to be included in each of the super blocks based on the performance grades, and write-access an opened super block, among the super blocks.
Claims20
A memory system comprising:
- a plurality of memory devices, each including a plurality of memory blocks;
- and
- a controller configured to evaluate performance grades of the plurality of memory blocks, form super blocks spanning the plurality of memory devices by selecting memory blocks, among the plurality of memory blocks, to be included in each of the super blocks based on the performance grades, and write-access an opened super block, among the super blocks.
A method for operating a memory system including a plurality of memory devices, each of which includes a plurality of memory blocks, the method comprising:
- evaluating performance grades of the plurality of memory blocks;
- forming super blocks spanning the plurality of memory devices by selecting memory blocks, among the plurality of memory blocks, to be included in each of the super blocks based on the performance grades;
- and
- write-accessing an opened super block among the super blocks.
A memory system comprising:
- a plurality of memory blocks, each including a plurality of memory units;
- and
- a controller configured to:
- evaluate operation conditions of the respective memory blocks based on operation conditions of the respective memory units;
- group two or more memory blocks, among the plurality of memory blocks, having similar operation conditions into super blocks to form at least a high performance super block having memory blocks of high operation conditions and a low performance super block having memory blocks of low operation conditions;
- and
- assign the high performance super block for an externally requested operation and the low performance super block for an internally requested operation.
Dependencies are inferred from the claim text.