Data protecting method, memory control circuit unit and memory storage apparatus
AssigneePhison Electronics Corp.
InventorChih-Kang Yeh
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Abstract
A data protecting method, a memory control circuit unit and a memory storage apparatus are provided. The method includes generating a first temporary parity code group based on first data written into a first super physical unit; generating a second temporary parity code group by performing a logic operation on second data written into a second super physical unit and the first temporary parity code group; and generating an updated parity code group by performing the logic operation on the second temporary parity code group and the first data when data of the first super physical unit all become invalid data.
Claims20
A data protecting method for a rewritable non-volatile memory module, the rewritable non-volatile memory module comprising a plurality of super physical units, the data protecting method comprising:
- writing first data into a first super physical unit among the super physical units;
- generating a first temporary parity code group based on the first data;
- writing second data into a second super physical unit among the super physical units;
- generating a second temporary parity code group by performing a logic operation on the second data and the first temporary parity code group;
- and
- generating an updated parity code group by performing the logic operation on the second temporary parity code group and the first data stored in the first super physical unit when data in the first super physical unit all become invalid data.
A memory control circuit unit, configured to control a rewritable non-volatile memory module, the memory control circuit unit comprising:
- a host interface, configured to electrically connect to a host system;
- a memory interface, configured to electrically connect to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of super physical units;
- and
- a memory management circuit, electrically connected to the host interface and the memory interface,
- wherein the memory management circuit is configured to write first data into a first super physical unit among the super physical units;
- wherein the memory management circuit is configured to generate a first temporary parity code group based on the first data;
- wherein the memory management circuit is configured to write second data into a second super physical unit among the super physical units;
- wherein the memory management circuit is configured to generate a second temporary parity code group by performing a logic operation on the second data and the first temporary parity code group;
- and
- wherein the memory management circuit is configured to generate an updated parity code group by performing the logic operation on the second temporary parity code group and the first data stored in the first super physical unit when data in the first super physical unit all become invalid data.
A memory storage apparatus, comprising:
- a connector, configured to electrically connect to a host system;
- a rewritable non-volatile memory module, comprising a plurality of super physical units;
- and
- a memory control circuit unit, electrically connected to the connector and the rewritable non-volatile memory module,
- wherein the memory control circuit unit is configured to write first data into a first super physical unit among the super physical units;
- wherein the memory control circuit unit is configured to generate a first temporary parity code group based on the first data;
- wherein the memory control circuit unit is configured to write second data into a second super physical unit among the super physical units;
- wherein the memory control circuit unit is configured to generate a second temporary parity code group by performing a logic operation on the second data and the first temporary parity code group;
- and
- wherein the memory control circuit unit is configured to generate an updated parity code group by performing the logic operation on the second temporary parity code group and the first data stored in the first super physical unit when data in the first super physical unit all become invalid data.
Dependencies are inferred from the claim text.