Inline ecc function for system-on-chip
AssigneeXilinx, Inc.
InventorsYgal Arbel, Ian A. Swarbrick, Sagheer Ahmad
Life of this patent
Estimating the term…
Abstract
An example integrated circuit (IC) includes a network-on-chip (NoC), a master device coupled to the NoC, a memory controller coupled to the NoC configured to control a memory coupled to the IC, and an inline error-correcting code (ECC) circuit coupled to the NoC. The ECC circuit is configured to receive read and write transactions from the master device that target the memory, compute ECC data based on the read and write transactions, and provide outgoing transactions to the memory controller.
Claims20
An integrated circuit (IC), comprising:
- a network-on-chip (NoC);
- a master device coupled to the NoC;
- a memory controller coupled to the NoC configured to control a memory coupled to the IC;
- and
- an inline error-correcting code (ECC) circuit coupled to the NoC, the ECC circuit configured to receive read and write transactions from the master device that target the memory, compute ECC data based on the read and write transactions, and provide outgoing transactions to the memory controller.
A method of memory management in an integrated circuit (IC), comprising:
- receiving a transaction from a master device at an inline error-correcting code (ECC) circuit through a network-on-chip (NoC), the transaction targeting a memory coupled to the IC;
- determining ECC data based on the transaction at the inline ECC circuit;
- and
- providing one or more outgoing transactions to a memory controller coupled to the NoC configured to control the memory.
An integrated circuit (IC), comprising:
- a processing system;
- a programmable logic region;
- a network-on-chip (NoC) coupling the processing system and the programmable logic region;
- a master device coupled to the NoC;
- a memory controller coupled to the NoC configured to control a memory coupled to the IC;
- and
- an inline error-correcting code (ECC) circuit coupled to the NoC, the ECC circuit configured to receive read and write transactions from the master device that target the memory, compute ECC data based on the read and write transactions, and provide outgoing transactions to the memory controller.
Dependencies are inferred from the claim text.