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US 2019/0196867 A1Published application
System and method of priority-based interrupt steering
AssigneeQUALCOMM Incorporated
InventorsErich Plondke, Suresh Kumar Venkumahanti, Lin Wang, Lucian Codrescu
Life of this patent
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Abstract
A processor includes priority adjustment circuitry configured to adjust a priority of a thread of multiple threads configured to execute tasks to have a software-defined priority value or a designated high priority value. The processor also includes circuitry configured to identify a lowest priority thread of the multiple threads and a control unit configured to cause the lowest priority thread to take a pending interrupt.
Claims20
A processor comprising:
- priority adjustment circuitry configured to adjust a priority of a thread of multiple threads configured to execute tasks, the priority adjustment circuitry configured to adjust the priority to have a software-defined priority value or a designated high priority value;
- a lowest priority thread detector configured to identify a lowest priority thread of the multiple threads;
- and
- a control unit configured to cause the lowest priority thread to take a pending interrupt.
1 more element
A method of operating a processor, the method comprising:
- adjust a priority of a thread of multiple threads to have a software-defined priority value or a designated high priority value;
- identifying a lowest priority thread of the multiple threads;
- and
- causing the lowest priority thread to take a pending interrupt.
1 more element
An apparatus comprising:
- means for adjusting a priority of a thread of multiple threads to have a software-defined priority value or a designated high priority value;
- means for identifying a lowest priority thread of the multiple threads;
- and
- means for causing the lowest priority thread to take a pending interrupt.
1 more element
Dependencies are inferred from the claim text.