System and method for increasing address generation operations per cycle

A processor for processing micro-operations, comprising:

• a micro-operation dispatch unit;
• a scheduler queue, the scheduler queue having a first set of entries and a second set of entries which are non-overlapped;
• a first picker;
• and
• a second picker,
• wherein:
• the micro-operation dispatch unit is configured to dispatch micro-operations to the scheduler queue,
• the first picker is configured to pick, in a picking cycle, an oldest micro-operation that is ready for issue from the first set of entries in the scheduler queue;
• the second picker is configured to pick, in the picking cycle, an oldest micro-operation that is ready for issue from the second set of entries in the scheduler queue;
• the scheduler queue is configured to issue, in the picking cycle, the picked micro-operation from the first set of entries;
• and
• the scheduler queue is configured to issue, in the picking cycle, the picked micro-operation from the second set of entries.

A method for processing micro-operations, the method comprising:

• dispatching micro-operations to at least one scheduler queue;
• picking, in a picking cycle, a first oldest micro-operation that is ready for issue from the at least one scheduler queue;
• picking, in the picking cycle, a second oldest micro-operation that is ready for issue from the at least one scheduler queue;
• picking, in the picking cycle, at least one further oldest micro-operation that is ready for issue from the at least one scheduler queue;
• issuing, in the picking cycle, the picked first oldest micro-operation;
• and
• issuing, in the picking cycle, the picked second oldest micro-operation.