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US 2019/0196830 A1Published application
Stacked transistors with different gate lengths in different device strata
AssigneeIntel Corporation
InventorsAaron D. Lilak, Gilbert W. Dewey, Willy Rachmady, Rishabh Mehandru, Ehren Mannebach, Cheng-Ying Huang, Anh Phan, Patrick Morrow
Life of this patent
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Abstract
Disclosed herein are stacked transistors with different gate lengths in different device strata, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, with two different device strata having different gate lengths.
Claims20
An integrated circuit (IC) structure, comprising:
- a first device stratum including a first channel material and a first gate, wherein the first gate has a first gate length;
- and
- a second device stratum including a second channel material and a second gate, wherein the second channel material is above and aligned with the first channel material, the second gate has a second gate length, and the first gate length is less than the second gate length.
An integrated circuit (IC) die, comprising:
- a first device stratum including a first channel material, a first gate, and first source/drain materials at opposing ends of the first channel material;
- a second device stratum including a second channel material, a second gate, and second source/drain materials at opposing ends of the second channel material;
- and
- a spacer structure between the first gate and the first source/drain materials and between the second gate and the second source/drain materials, wherein the spacer structure has a first thickness between the first gate and the first source/drain materials, the spacer structure has a second thickness between the second gate and the second source/drain materials, and the first thickness is greater than the second thickness.
1 more element
A computing device, comprising:
- a circuit board;
- and
- an integrated circuit (IC) package coupled to the circuit board, wherein the IC package includes a package substrate and an IC die coupled to the package substrate, the IC die includes stacked strata of transistors, and a first device stratum has a first gate length that is less than a second gate length of a second device stratum.
Dependencies are inferred from the claim text.