Apparatus and method for vector multiply and subtraction of signed doublewords

A method comprising:

• decoding an instruction, the instruction including an opcode, and operands identifying a plurality of packed data source registers and a packed data destination register
• executing the decoded instruction by:
• multiplying first and second packed signed doubleword data elements from a first source register with third and fourth packed signed doubleword data elements from a second source register, respectively, to generate first and second temporary signed quadword products, the first, second, third, and fourth signed doubleword data elements to be selected based on the opcode of the instruction,
• negating the first and second temporary signed quadword products to generate first and second negated signed quadword products,
• accumulating the first negated signed quadword product with a first packed signed quadword value read from a third source register to generate a first accumulated signed quadword result and accumulating the second negated signed quadword product with a second packed signed quadword value read from the third source register to generate a second accumulated signed quadword result, and
• storing the first accumulated signed quadword result in a first signed quadword data element position in a destination register or the third source register and storing the second accumulated signed quadword result in a second signed quadword data element position in the destination register or the third source register.

A machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of:

• decoding an instruction, the instruction including an opcode, and operands identifying a plurality of packed data source registers and a packed data destination register
• executing the decoded instruction by:
• multiplying first and second packed signed doubleword data elements from a first source register with third and fourth packed signed doubleword data elements from a second source register, respectively, to generate first and second temporary signed quadword products, the first, second, third, and fourth signed doubleword data elements to be selected based on the opcode of the instruction,
• negating the first and second temporary signed quadword products to generate first and second negated signed quadword products,
• accumulating the first negated signed quadword product with a first packed signed quadword value read from a third source register to generate a first accumulated signed quadword result and accumulating the second negated signed quadword product with a second packed signed quadword value read from the third source register to generate a second accumulated signed quadword result, and
• storing the first accumulated signed quadword result in a first signed quadword data element position in a destination register or the third source register and storing the second accumulated signed quadword result in a second signed quadword data element position in the destination register or the third source register.