US 2019/0196828 A1 · APPARATUS AND METHOD FOR VECTOR MULTIPLY OF SIGNED WORDS, ROUNDING, AND SATURATION

Abstract

An apparatus and method for performing signed fractional multiplication of packed data elements. For example one embodiment of a processor comprises: a decoder to decode an instruction; a first source register to store a first plurality of packed signed word data elements; a second source register to store a second plurality of packed signed word data elements; a control register to store a rounding control value to indicate a rounding mode; execution circuitry to execute the decoded instruction, the execution circuitry comprising: multiplier circuitry to concurrently multiply each of the packed signed word data elements of the first plurality with a corresponding packed signed word data element of the second plurality to generate a plurality of signed doubleword products; conversion circuitry to convert the plurality of signed doubleword products to a plurality of fractional signed words, the conversion circuitry including rounding circuitry to round the signed doubleword products in accordance with the rounding mode indicated by the rounding control value to generate the plurality of fractional signed words; and a destination register to store the plurality of fractional signed words as packed signed word fractional data elements in specified data element positions within the destination register.

Claims24

Dependent claims

A processor comprising:

a decoder to decode an instruction;
a first source register to store a first plurality of packed signed word data elements;
a second source register to store a second plurality of packed signed word data elements;
a control register to store a rounding control value to indicate a rounding mode;
execution circuitry to execute the decoded instruction, the execution circuitry comprising:
multiplier circuitry to concurrently multiply each of the packed signed word data elements of the first plurality with a corresponding packed signed word data element of the second plurality to generate a plurality of signed doubleword products;
conversion circuitry to convert the plurality of signed doubleword products to a plurality of fractional signed words, the conversion circuitry including rounding circuitry to round the signed doubleword products in accordance with the rounding mode indicated by the rounding control value to generate the plurality of fractional signed words;
and
a destination register to store the plurality of fractional signed words as packed signed word fractional data elements in specified data element positions within the destination register.

6 more elements

A method comprising:

decoding an instruction;
executing the instruction to perform the operations of:
concurrently multiplying each of a plurality of packed signed word data elements of a first plurality stored in a first source register with a corresponding packed signed word data element of a second plurality stored in a second source register to generate a plurality of signed doubleword products;
converting the plurality of signed doubleword products to a plurality of fractional signed words, wherein converting includes to rounding the signed doubleword products in accordance with a rounding mode indicated by a rounding control value stored in a control register to generate the plurality of fractional signed words;
and
storing the plurality of fractional signed words as packed signed word fractional data elements in specified data element positions within the destination register.

3 more elements

A machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of:

decoding an instruction;
executing the instruction to perform the operations of:
concurrently multiplying each of a plurality of packed signed word data elements of a first plurality stored in a first source register with a corresponding packed signed word data element of a second plurality stored in a second source register to generate a plurality of signed doubleword products;
converting the plurality of signed doubleword products to a plurality of fractional signed words, wherein converting includes to rounding the signed doubleword products in accordance with a rounding mode indicated by a rounding control value stored in a control register to generate the plurality of fractional signed words;
and
storing the plurality of fractional signed words as packed signed word fractional data elements in specified data element positions within the destination register.

3 more elements

Dependencies are inferred from the claim text.

Apparatus and method for vector multiply of signed words, rounding, and saturation

Life of this patent

Apparatus and method for vector multiply of signed words, rounding, and saturation

Life of this patent

Abstract

Claims24