Vector multiply-add instruction

An apparatus comprising:

• processing circuitry to perform data processing;
• a plurality of vector registers to store vector values comprising a plurality of data elements;
• a plurality of scalar registers to store scalar values;
• and
• an instruction decoder to decode a vector multiply-add instruction specifying a plurality of registers including at least one vector register and at least one scalar register, to control the processing circuitry to perform a vector multiply-add operation comprising a plurality of lanes of processing on a first vector value stored in a first vector register specified by the vector multiply-add instruction to generate a result vector value comprising a plurality of result data elements;
• each lane of processing comprising generating a respective result data element of the result vector value corresponding to a sum or difference of a product value and an addend value, the product value corresponding to a product of a respective data element of the first vector value and a multiplier value;
• wherein for each lane of processing, at least one of the multiplier value and the addend value comprises at least a portion of a scalar value stored in a scalar register specified by the vector multiply-add instruction.