Apparatus and method for vector horizontal add of signed/unsigned words and doublewords

A processor comprising:

• a decoder to decode an instruction to generate a decoded packed horizontal add instruction, the instruction including an opcode and operands identifying a plurality of packed doublewords;
• a source register to store a first plurality of packed doublewords;
• execution circuitry to execute the decoded instruction, the execution circuitry comprising:
• operand selection circuitry to identify first and second packed doublewords from the source register in accordance with the operand and opcode of the packed horizontal add instruction,
• adder circuitry to add the first and second packed doublewords to generate a temporary sum,
• a temporary storage of at least 33 bits to store the temporary sum, and
• saturation circuitry to saturate the temporary sum if necessary to generate a final result;
• a destination register to store the final result as a packed result doubleword in a designated data element position.

A method comprising:

• decoding an instruction, the instruction including an opcode and operands identifying a plurality of packed words;
• storing a first plurality of packed words in a source register;
• executing the decoded instruction to perform the operations of:
• identifying first and second packed words from the source register in accordance with the operand and opcode of the packed horizontal add instruction,
• adding the first and second packed words to generate a temporary sum,
• storing the temporary sum in a temporary storage of at least 17 bits,
• saturating the temporary sum if necessary to generate a final result, and
• storing the final result as a packed result word in a designated data element position of a destination register.

A machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of:

• decoding an instruction, the instruction including an opcode and operands identifying a plurality of packed words;
• executing the decoded instruction to perform the operations of:
• identifying first and second packed words from a source register in accordance with the operand and opcode of the packed horizontal add instruction,
• adding the first and second packed words to generate a temporary sum,
• storing the temporary sum in a temporary storage of at least 17 bits,
• saturating the temporary sum if necessary to generate a final result, and
• storing the final result as a packed result word in a designated data element position of a destination register.