# US 2019/0196819 A1 · Apparatus and method for left-shifting packed quadwords and extracting packed doublewords > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0196819 A1 - Document ID: US20190196819A1 - Status: Published application - Kind: A1 - Application number: 15/850,716 - Filed: 2017-12-21 - Published: 2019-06-27 - Earliest claimed: 2017-12-21 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: VENKATESWARA MADDURI; ELMOUSTAPHA OULD-AHMED-VALL; ROBERT VALENTINE; MARK CHARNEY - Web page: https://patentgrep.com/patent/US20190196819A1 ## CPC - G06F 9/30032: {Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE} - G06F 9/3001: {Arithmetic instructions} - G06F 9/30014: {with variable precision} - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/30038: {using a mask} - G06F 9/30098: {Register arrangements} - G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An apparatus and method for performing right-shifting operations on packed quadword data. For example, one embodiment of a processor comprises: a decoder to decode a left-shift instruction to generate a decoded left-shift instruction; a first source register to store a plurality of packed quadword data elements, each of the packed quadword data elements including a sign bit; execution circuitry to execute the decoded left-shift instruction, the execution circuitry comprising shift circuitry with sign preservation logic to left-shift first and second packed quadword data elements from first and second packed quadword data element locations, respectively, in the first source register by an amount specified in an immediate value or in a control value in a second source register, the left-shifting to generate first and second left-shifted quadwords, the shift circuitry to write zeroes into bit positions exposed by the left-shifting of the packed quadword data elements; the sign preservation logic to maintain a copy of the sign bit while the shift circuitry performs the left-shift operations; the execution circuitry to cause selection of 32 most significant bits of the first and second left-shifted quadwords, including the sign bit, to be written to 32 least significant bit regions of first and second quadword data element locations, respectively, of a destination register, writing the sign bit to the most significant bit position of each 32 least significant bit region. ## Claims ### Claim 1 A processor comprising: a decoder to decode an instruction; a first source register to store a plurality of packed quadword data elements, each of the packed quadword data elements including a sign bit; execution circuitry to execute the decoded instruction, the execution circuitry comprising shift circuitry with sign preservation logic to left-shift first and second packed quadword data elements from first and second packed quadword data element locations, respectively, in the first source register by an amount specified in an immediate value or in a control value in a second source register, the left-shifting to generate first and second left-shifted quadwords, the shift circuitry to write zeroes into bit positions exposed by the left-shifting of the packed quadword data elements; the sign preservation logic to maintain a copy of the sign bit while the shift circuitry performs the left-shift operations; the execution circuitry to cause selection of 32 most significant bits of the first and second left-shifted quadwords, including the sign bit, to be written to 32 least significant bit regions of first and second quadword data element locations, respectively, of a destination register, writing the sign bit to the most significant bit position of each 32 least significant bit region. ### Claim 2 (depends on 1) The processor of claim 1 further comprising: rounding circuitry to perform a rounding operation on the 32 most significant bits of the first and second left-shifted quadwords in accordance with a rounding mode specified in a control register. ### Claim 3 (depends on 2) The processor of claim 2 further comprising: saturation circuitry to saturate values encoded in the 32 most significant bits of the first and second left-shifted quadwords prior to storage in the destination register. ### Claim 4 (depends on 3) The processor of claim 3 wherein one or more saturation flags are to be updated responsive to the 32 most significant bits of the first and second left-shifted quadwords being saturated. ### Claim 5 (depends on 1) The processor of claim 1 wherein the 32 most significant bits of the first and second left-shifted quadwords comprise all values of the sign bit if the amount specified in the immediate value or in the control value is above a threshold number. ### Claim 6 (depends on 1) The processor of claim 1 wherein the immediate value or control value of the second source register comprises a 6-bit value to indicate the shift amount. ### Claim 7 (depends on 1) The processor of claim 1 wherein the first source register and destination register comprise 128-bit packed data registers. ### Claim 8 (depends on 7) The processor of claim 7 wherein the 128-bit packed data registers comprise xmm registers. ### Claim 9 A method comprising: decoding an instruction; storing a plurality of packed quadword data elements in a first source register, each of the packed quadword data elements including a sign bit; executing the decoded instruction, wherein executing the decoded instruction comprises: left-shifting first and second packed quadword data elements from first and second packed quadword data element locations, respectively, in the first source register by an amount specified in an immediate value or in a control value in a second source register, the left-shifting to generate first and second left-shifted quadwords, wherein each of the packed quadword data elements including a sign bit, writing zeroes into bit positions exposed by the left-shifting of the packed quadword data elements, maintaining a copy of the sign bit while the shift circuitry performs the left-shift operations, and selecting 32 most significant bits of the first and second left-shifted quadwords, including the sign bit, to be written to 32 least significant bit regions of first and second quadword data element locations, respectively, of a destination register, writing the sign bit to the most significant bit position of each 32 least significant bit region. ### Claim 10 (depends on 9) The method of claim 9 further comprising: performing a rounding operation on the 32 most significant bits of the first and second left-shifted quadwords in accordance with a rounding mode specified in a control register. ### Claim 11 (depends on 10) The method of claim 10 further comprising: saturating values encoded in the 32 most significant bits of the first and second left-shifted quadwords prior to storage in the destination register. ### Claim 12 (depends on 11) The method of claim 11 wherein one or more saturation flags are to be updated responsive to the 32 most significant bits of the first and second left-shifted quadwords being saturated. ### Claim 13 (depends on 9) The method of claim 9 wherein the 32 most significant bits of the first and second left-shifted quadwords comprise all values of the sign bit if the amount specified in the immediate value or in the control value is above a threshold number. ### Claim 14 (depends on 9) The method of claim 9 wherein the immediate value or control value of the second source register comprises a 6-bit value to indicate the shift amount. ### Claim 15 (depends on 9) The method of claim 9 wherein the first source register and destination register comprise 128-bit packed data registers. ### Claim 16 (depends on 15) The method of claim 15 wherein the 128-bit packed data registers comprise xmm registers. ### Claim 17 A machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of: decoding an instruction; storing a plurality of packed quadword data elements in a first source register, each of the packed quadword data elements including a sign bit; executing the decoded instruction, wherein executing the decoded instruction comprises: left-shifting first and second packed quadword data elements from first and second packed quadword data element locations, respectively, in the first source register by an amount specified in an immediate value or in a control value in a second source register, the left-shifting to generate first and second left-shifted quadwords, wherein each of the packed quadword data elements including a sign bit, writing zeroes into bit positions exposed by the left-shifting of the packed quadword data elements, maintaining a copy of the sign bit while the shift circuitry performs the left-shift operations, and selecting 32 most significant bits of the first and second left-shifted quadwords, including the sign bit, to be written to 32 least significant bit regions of first and second quadword data element locations, respectively, of a destination register, writing the sign bit to the most significant bit position of each 32 least significant bit region. ### Claim 18 (depends on 17) The machine-readable medium of claim 17 further comprising program code to cause the machine to perform the operation of: performing a rounding operation on the 32 most significant bits of the first and second left-shifted quadwords in accordance with a rounding mode specified in a control register. ### Claim 19 (depends on 18) The machine-readable medium of claim 18 further comprising program code to cause the machine to perform the operation of: saturating values encoded in the 32 most significant bits of the first and second left-shifted quadwords prior to storage in the destination register. ### Claim 20 (depends on 19) The machine-readable medium of claim 19 wherein one or more saturation flags are to be updated responsive to the 32 most significant bits of the first and second left-shifted quadwords being saturated. ### Claim 21 (depends on 17) The machine-readable medium of claim 17 wherein the 32 most significant bits of the first and second left-shifted quadwords comprise all values of the sign bit if the amount specified in the immediate value or in the control value is above a threshold number. ### Claim 22 (depends on 17) The machine-readable medium of claim 17 wherein the immediate value or control value of the second source register comprises a 6-bit value to indicate the shift amount. ### Claim 23 (depends on 17) The machine-readable medium of claim 17 wherein the first source register and destination register comprise 128-bit packed data registers. ### Claim 24 (depends on 23) The machine-readable medium of claim 23 wherein the 128-bit packed data registers comprise xmm registers.