Multiple-pipeline architecture with special number detection
AssigneeAlibaba Group Holding Limited
InventorsLiang HAN, Xiaowei JIANG
Life of this patent
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Abstract
The present disclosure relates to a computing device with a multiple pipeline architecture. The multiple pipeline architecture comprises a first and second pipeline for which are concurrently running, where the first pipeline runs at least one cycle ahead of the second pipeline. Special number detection is utilized on the first pipeline, where a special number is a numerical value which yields a predictable result. Upon the detection of a special number, a computation is optimized.
Claims20
A method for computation, with special number detection, in a computational device having a core with a multiple-pipeline architecture, the method comprising:
- running, in parallel, a first and second pipeline of data from a memory, wherein the first pipeline is configured to receive a first operand from the memory and the second pipeline is configured to receive a second operand from the memory, and wherein the first pipeline operates at least one cycle ahead of the second pipeline;
- generating a memory address in the memory for the first operand;
- reading, on the first pipeline, the first operand from the generated memory address;
- and
- detecting if the first operand is a special number, wherein a special number is a numerical value that yields a predictable operation result;
- and
- storing a result in the memory based on the detection of whether the first operand is the special number.
A computational device for performing an operation with special number detection, the computational device comprising:
- a core having a plurality of processing units configured to perform operations, the core comprising:
- a memory configured to store operands;
- a first pipeline configured to read a first operand from the memory based on a memory address being generated for the first operand;
- a second pipeline configured to receive a second operand from the memory, wherein the first pipeline operates at least one cycle ahead of the second pipeline;
- a detector configured to detect if the first operand is a special number, wherein the special number is a numerical value that yields a predictable operation result and wherein the core is further configured to store a result in the memory based on the detection whether the first operand is a special number.
A non-transient computer readable medium that stores a set of instructions that is executable by a computational device to cause a core of the computational device to:
- run, in parallel, a first and second pipeline of data from the memory of the core, wherein the first pipeline is configured to receive a first operand from the memory and the second pipeline is configured to receive a second operand from the memory, and wherein the first pipeline operates at least one cycle ahead of the second pipeline;
- generate a memory address in the memory for the first operand;
- read, on the first pipeline, the first operand from the generated memory address;
- detect if the first operand is a special number, wherein a special number is a numerical value which yields a predictable operation result;
- and
- store, in the memory, a result based on the detection whether the first operation is the special number.
Dependencies are inferred from the claim text.