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AssigneeIntel Corporation
InventorsVENKATESWARA MADDURI, ELMOUSTAPHA OULD-AHMED-VALL, ROBERT VALENTINE, MARK CHARNEY, JESUS CORBAL
Estimating the term…
An apparatus and method for performing multiplication, summation, negation, sign extension, and accumulation with packed bytes. For example, one embodiment of a processor comprises: a decoder to decode an instruction to generate a decoded instruction, the instruction including an opcode, and a plurality of operands identifying a plurality of packed data source registers and a packed data destination register; a first source register to store a first plurality of packed signed bytes; a second source register to store a second plurality of packed signed bytes; execution circuitry to execute the decoded instruction, the execution circuitry comprising: multiplier circuitry to multiply each packed signed byte from the first source register with a corresponding packed signed byte from the second source register to generate a plurality of temporary products, adder circuitry to add a plurality of sets of the temporary products to generate a plurality of temporary sums; negation and extension circuitry to negate and extend each of the temporary sums to doublewords sums; and accumulation circuitry to add each of the doublewords sums to a doubleword from a third source register to general final doubleword results; and a packed data destination register to store the final doubleword results in specified data element locations.
A processor comprising:
A method comprising:
A machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of:
Dependencies are inferred from the claim text.