Mixed-precision floating-point arithmetic circuitry in specialized processing blocks

An integrated circuit device that generates a dot product from a plurality of vectors, comprising:

• a plurality of specialized processing blocks that each comprises:
• a plurality of inputs that receives at least a portion of a plurality of vectors having a first floating point precision level,
• arithmetic circuitry generates a partial product based on quaternary reduction of two tuples from each of two vectors of the plurality of vectors, wherein each of the partial products has a second floating point precision level, wherein the second floating point precision level is higher than the first floating point precision level;
• and
• a cast function circuit to reduce each of the partial products to the first floating point precision level;
• one or more cascade connections to pass one or more of the partial products to a summing specialized processing block of the plurality of specialized processing blocks including an adder that adds the one or more partial products to a partial product of the partial products corresponding to the one or more cascade connections;
• and
• an output to output the dot product.

A method for operating an integrated circuit that generates a dot product of first and second vectors, comprising:

• generating a first partial product with a first specialized processing block based on a first reduction of tuples of the first and second vector, wherein the first and second vectors both have a first floating-point precision level, and the first partial product has a second floating-point precision level;
• transmitting the first partial product at a cascade output of the first specialized processing block to a cascade input of a second floating-point precision level;
• generating a second partial product with the second specialized processing block based on a second reduction of the first and second vector, wherein the second partial product has a second floating-point precision level;
• and
• generating the dot product by performing a binary reduction of the first and second partial products in the second specialized processing block.

A tangible, non-transitory, and computer-readable medium encoded with instructions for configuring first and second specialized processing blocks of an integrated circuit to generate a dot product of first and second vectors, wherein the instructions are configured to cause a processor to:

• configure the first specialized processing block to generate a first partial product based on a first quaternary reduction of tuples of the first and second vector, wherein the first and second vectors both have a first floating-point precision level, and the first partial product has a second floating-point precision level;
• configured the first and second specialized processing blocks to transmit the first partial product at a cascade output of the first specialized processing block to a cascade input of a second floating-point precision level;
• configure the second specialized processing block to generate a second partial product based on a second quaternary reduction of tuples of the first and second vector, wherein the second partial product has a second floating-point precision level;
• and
• configure the second specialized processing block to generate the dot product by performing a binary reduction of the first and second partial products in the second specialized processing block.