Extreme-bandwidth scalable performance-per-watt gpu architecture

A control die for accessing data of a stacked accelerated processing device (“APD”) memory, the control die comprising:

• a plurality of selectors coupled to a plurality of APD through-silicon-vias (“TSVs”) and to a plurality of bitline TSVs (“BLTSVs”);
• and
• a controller configured to:
• receive an address and an access type for a memory access request from an execution unit;
• identify memory cells in stacked memory dies associated with the address;
• determine that the identified memory cells include at least one memory cell deemed to be local to the execution unit;
• and
• responsive to the determining, access the local memory cells via the BLTSVs without using a bus.

A stacked accelerated processing device (“APD”) and memory device comprising:

• a plurality of stacked memory dies;
• an APD;
• and
• a control die for accessing data of the plurality of memory dies, the control die comprising:
• a plurality of selectors coupled to a plurality of APD through-silicon-vias (“TSVs”) and to a plurality of bitline TSVs (“BLTSVs”), the plurality of APD TSVs coupled to the plurality of stacked memory dies and the plurality of BLTSVs coupled to the APD;
• and
• a controller configured to:
• receive an address and an access type for a memory access request from an execution unit of the APD;
• identify memory cells in the plurality of stacked memory dies associated with the address;
• determine that the identified memory cells include at least one memory cell deemed to be local to the execution unit;
• and
• responsive to the determining, access the local memory cells via the BLTSVs without using a bus.