Systems and methods for reducing performance state change latency
AssigneeApple Inc.
InventorsRakesh L. Notani, Robert E. Jeter
Life of this patent
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Abstract
A method and apparatus for performing performance state changes are disclosed. A power management circuit may be configured to receive requests for changes to first and second performance states for at least at least one memory of a plurality of memories. In response to a determination that a change to the first performance state is in progress, when the request to change to the second performance state is received, the power management controller may send a notification to a controller coupled to the memories. The controller may halt scheduling of memory interface calibration operations for the at least one memory based on the notification.
Claims20
An apparatus, comprising:
- a plurality of memories;
- a controller coupled to the plurality of memories;
- and
- a power management circuit configured to:
- receive a request for a change to a first performance state for at least one memory of the plurality of memories;
- receive a request for a change to a second performance state for the at least one memory, wherein the request for the change to the second performance state is received after the request for the change to the first performance state;
- send a notification to the controller, in response to a determination that the change to the first performance state is in progress;
- and
- execute the change to the second performance state upon completion of the change to the first performance state;
- and
- wherein the controller is configured to halt scheduling of memory interface calibration operations for the at least one memory based on the notification.
A method, comprising:
- receiving, by a power management circuit, a request for a change to a first performance state for at least one memory of a plurality of memories;
- receiving, by the power management circuit, a request for a change to a second performance state for the at least one memory, wherein the request for the change to the second performance state is received after the request for the change to the first performance state;
- sending, by the power management circuit, in response to determining the change to the first performance state is in progress, a notification to a controller coupled to the plurality of memories;
- halting, by the controller, scheduling of memory interface calibration operation for the at least one memory based on the notification;
- and
- executing the change to the second performance state for the at least one memory upon completion of the change to the first performance state.
A non-transitory computer-readable storage medium having design information stored thereon, wherein the design information specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the hardware integrated circuit according to the design information, wherein the design information specifies that the hardware integrated circuit comprises:
- a plurality of memories;
- a controller coupled to the plurality of memories;
- and
- a power management circuit configured to:
- receive a request for a change to a first performance state for at least one memory of the plurality of memories;
- receive a request for a change to a second performance state for the at least one memory, wherein the request for the change to the second performance state is received after the request for the change to the first performance state;
- send a notification to the controller, in response to a determination that the change to the first performance state is in progress;
- and
- execute the change to the second performance state upon completion of the change to the first performance state;
- and
- wherein the controller is configured to halt scheduling of memory interface calibration operations for the at least one memory based on the notification.
Dependencies are inferred from the claim text.