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US 2019/0196722 A1Published application
Host device to embedded multi-media card device communication
AssigneesNXP B.V., NXP USA, Inc.
InventorsBIN ER, Wenwei Jiang, Xiaodong Niu, Yan Song
Life of this patent
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Abstract
A host device includes a first serial peripheral interface (SPI) and a second SPI to communicate with an embedded multimedia card (eMMC) device. The host device has a mode controller that controls the first SPI to toggle between first transmission and first reception modes for command transmission and response reception, respectively. The mode controller controls the second SPI to toggle between second transmission and second reception modes for data transmission and data reception, respectively.
Claims23
A host device that communicates with an embedded multimedia card (eMMC) device, the host device comprising:
- a first serial peripheral interface (SPI) that has a command output terminal SPI1 MOSI connected to a command terminal CMD of the eMMC device for transmitting at least one of a data-write command to execute a data-write operation on the eMMC device and a data-read command to execute a data-read operation on the eMMC device, a response input terminal SPI1 MISO connected to the command terminal CMD for receiving a response to the at least one of the data-write command and the data-read command, a first clock terminal SPI1 CLK, and a first chip-select terminal SPI1 CS, wherein the first SPI is operable in one of first transmission and first reception modes;
- a second SPI that has a data output terminal SPI2 MISO connected to a data terminal DO of the eMMC device for transmitting write-data to the eMMC device based on the data-write command, a data input terminal SPI2 MOSI connected to the data terminal DO for receiving read-data from the eMMC device based on the data-read command, a second clock terminal SPI2 CLK, and a second chip-select terminal SPI2 CS, wherein the second SPI is operable in one of second transmission and second reception modes;
- a mode controller, connected to the first and second SPIs, that enables the first SPI to operate in the first transmission mode and the first reception mode, and the second SPI to operate in the second transmission mode and the second reception mode, based on the data-read and data-write commands;
- and
- first and second resistors that act as fail-safe resistors for preventing an open circuit condition of the command and data channels.
2 more elements
A host device for communication with an embedded multimedia card (eMMC) device, the host device comprising:
- a first serial peripheral interface (SPI) having a command output terminal SPI1 MOSI connected to a first terminal of the eMMC device for transmitting at least one of a data-write command to execute a data-write operation on the eMMC device and a data-read command to execute a data-read operation on the eMMC device, and a response input terminal SPI1 MISO connected to the first terminal of the eMMC device for receiving a response to the at least one of the data-write command and the data-read command, wherein the first SPI is operable in one of a first transmission mode and a first reception mode;
- a second SPI having a data output terminal SPI2 MISO connected to a second terminal of the eMMC device for transmitting write-data based on the data-write command to the eMMC device, and a data input terminal SPI2 MOSI connected to the second terminal of the eMMC device for receiving read-data from the eMMC device, based on the data-read command, wherein the second SPI is operable in one of a second transmission mode and a second reception mode;
- a first control register having a first reserved bit for enabling the first SPI to operate in one of the first transmission mode and the first reception mode, and a second reserved bit for enabling the second SPI to operate in one of the second transmission mode and the second reception mode;
- a mode controller that sets a value of the first and second reserved bits based on at least one of the data-write command and the data-read command, thereby enabling the first and second SPIs to operate in one of the first transmission mode and the first reception mode, and one of the second transmission mode and the second reception mode, respectively;
- and
- first and second resistors that act as fail-safe resistors for preventing an open circuit condition of the command and data channels.
3 more elements
An integrated circuit, comprising:
- a host device comprising a first serial peripheral interface (SPI) having a command output terminal SPI1 MOSI and a response input terminal SPI1 MISO, and a second SPI having a data output terminal SPI2 MISO and a data input terminal SPI2 MOSI, a first clock terminal SPI1 CLK, and a first chip-select terminal SPI1 CS;
- and
- an embedded multimedia card (eMMC) device connected to the host device, wherein the eMMC device includes (i) a memory array for storing data received from the host device;
- (ii) a first terminal connected to the command output terminal SPI1 MOSI of the first SPI for receiving data-read and data-write commands from the host device, and for transmitting a response to the host device, and (iii) a second terminal connected to the data input terminal SPI2 MOSI and data output terminal SPI2 MISO of the second SPI, wherein the eMMC device transmits read-data read from the memory array to the host device in response to a data-read command, and the host device transmits write-data to the eMMC for storing in the memory array in response to a write-data command,
- wherein the first SPI is operable in first transmission and first reception modes, and the second SPI is operable in second transmission and second reception modes, and
- wherein the host device further comprises a mode controller that causes the first SPI to operate in one of the first transmission and first reception modes, and the second SPI to operate in one of the second transmission and second reception modes, based on the data-read and data-write commands, and
- wherein the host device further comprises first and second resistors that act as fail-safe resistors for preventing an open circuit condition of the command and data channels.
4 more elements
Dependencies are inferred from the claim text.