Scheduling memory requests for a ganged memory device
AssigneeAdvanced Micro Devices, Inc.
InventorJames Raymond Magro
Life of this patent
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Abstract
Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. A computing system includes one or more clients for processing applications. A memory controller transfers traffic between the memory controller and two channels, each connected to a memory device. A client sends a 64-byte memory request with an indication specifying that there are two 32-byte requests targeting non-contiguous data within a same page. The memory controller generates two addresses, and sends a single command and the two addresses to two channels to simultaneously access non-contiguous data in a same page.
Claims20
A memory controller comprising:
- a first interface for receiving memory requests;
- a second interface comprising:
- a command bus for sending memory access commands corresponding to the memory requests to a memory device;
- a first address bus for sending addresses to the memory device;
- and
- a second address bus for sending addresses to the memory device;
- control logic, wherein in response to determining a given memory access command is scheduled to be issued at a given point in time, the control logic is configured to:
- send the given memory access command to the memory device at the given point in time;
- send a first address on the first address bus at the given point in time, wherein the first address points to a first location in the memory device storing first data;
- and
- send a second address on the second address bus at the given point in time, wherein the second address points to a second location in the memory device storing second data that is non-contiguous with the first data.
A method, comprising:
- receiving, by a first interface, memory requests;
- sending, by a command bus in a second interface, memory access commands corresponding to the memory requests to a memory device;
- sending, by a first address bus in the second interface, addresses to the memory device;
- sending, by a second address bus in the second interface, addresses to the memory device;
- in response to determining a given memory access command is scheduled to be issued at a given point in time:
- sending at the given point in time the given memory access command to the memory device;
- sending at the given point in time a first address on the first address bus, wherein the first address points to a first location in the memory device storing first data;
- and
- sending at the given point in time a second address on the second address bus, wherein the second address points to a second location in the memory device storing second data that is non-contiguous with the first data.
A computing system comprising:
- a processor configured to generate memory access requests for data stored in a memory device;
- and
- a memory controller coupled to the memory device;
- wherein in response to determining a given memory access command is scheduled to be issued at a given point in time, the memory controller is configured to:
- send at the given point in time the given memory access command to the memory device;
- send at the given point in time a first address on the first address bus, wherein the first address points to a first location in the memory device storing first data;
- and
- send at the given point in time a second address on the second address bus, wherein the second address points to a second location in the memory device storing second data that is non-contiguous with the first data.
Dependencies are inferred from the claim text.