Self-timed clocked processor architecture

A self-timed clocked synchronous processor comprising:

• a combinatorial logic (CL) block operated at a speed dependent upon an operating voltage of the processor, the CL block having:
• CL logic to process CL input data signals received from a first register using CL data process values, the CL logic having a critical path with propagation delay between receiving the input data and outputting data to a second register that is a minimum allowable clock period to perform data processing of the CL logic at the operating voltage of the processor without a timing error;
• a critical path oscillator operated at a speed dependent upon the operating voltage of the processor and having:
• an oscillator output to output an oscillator clock signal to clock the first register, the second register and a power manager, the oscillator clock signal having a period that is greater than the minimum allowable clock period;
• and
• the power manager having:
• a bias voltage generator to output the operating voltage of the processor based on the oscillator clock signal and an external time reference signal.

A method of processing data within a self-timed clocked synchronous processor comprising:

• operating a combinatorial logic (CL) block at an operating voltage of the processor to process CL input data signals from a first register using CL data process values and to provide CL output data signals from the CL block to a second register, the CL block having a critical path that operates at the operating voltage with a propagation delay that is a minimum allowable clock period to perform data processing of the CL block of the processor without a timing error;
• operating a critical path oscillator at the operating voltage of the processor to output an oscillator clock signal with a period that is greater than the minimum allowable clock period to clock the first register, the second register and a power manager;
• and
• operating the power manager to output the operating voltage of the processor based on the oscillator clock signal and an external time reference signal.