Optical sensor and electronic device

An optical sensor comprising:

• a light emitting device;
• a first light-receiving unit of a photon count-type configured to output a pulse synchronous with photon incidence caused by reflected light from a sensing target;
• a second light-receiving unit of a photon count-type disposed closer to the light emitting device than the first light-receiving unit is, the second light-receiving unit being configured to output a pulse synchronous with photon incidence caused by reflected light in a sensor package;
• a time difference extraction circuit including a first DLL circuit configured to receive a pulse output from the first light-receiving unit and a reference clock and a second DLL circuit configured to receive a pulse output from the second light-receiving unit and the reference clock, the time difference extraction circuit being configured to extract a time difference corresponding to a distance on a spatial optical path;
• and
• an initial configuration circuit configured to give an initial phase value to the first DLL circuit, wherein
• the initial configuration circuit includes
• a means for giving an initial phase value of the first DLL circuit within a region including first to nth regions obtained by dividing each of cycles of the reference clock into n equal parts, where n is an integer larger than or equal to 2,
• a counter configured to perform counting of the number of pulse outputs from the first light-receiving unit in the first to nth regions, and
• a comparator for results of the counting,
• the initial configuration circuit determines by the comparator, a region in which a counter value is largest among the first to nth regions,
• the initial configuration circuit generates a phase configuration pulse signal for setting, as the initial phase value, a phase value corresponding to a case where a center of a received-light waveform of the reflected light received by the first light-receiving unit from the sensing target is located at a center position in the region determined,
• the initial configuration circuit gives the phase configuration pulse signal to the first DLL circuit,
• the initial configuration circuit outputs, as the phase configuration pulse signal, a signal cyclically achieving a High voltage in the region in which the counter value is largest to a pulse width increasing circuit, and
• the pulse width increasing circuit outputs a signal obtained by adding a prescribed width to a width of the phase configuration pulse signal to the first DLL circuit to cause the first DLL circuit to perform a converging operation to the region determined.

An optical sensor comprising:

• a light emitting device;
• a first light-receiving unit of a photon count-type configured to output a pulse synchronous with photon incidence caused by reflected light from a sensing target;
• a second light-receiving unit of a photon count-type disposed closer to the light emitting device than the first light-receiving unit is, the second light-receiving unit being configured to output a pulse synchronous with photon incidence caused by reflected light in a sensor package;
• a time difference extraction circuit including a first DLL circuit configured to receive a pulse output from the first light-receiving unit and a reference clock and a second DLL circuit configured to receive a pulse output from the second light-receiving unit and the reference clock, the time difference extraction circuit being configured to extract a time difference corresponding to a distance on a spatial optical path;
• and
• an initial configuration circuit configured to give an initial phase value to the first DLL circuit, wherein
• the initial configuration circuit includes
• a means for giving an initial phase value of the first DLL circuit within a region including first to nth regions obtained by dividing each of cycles of the reference clock into n equal parts, where n is an integer larger than or equal to 2,
• a counter configured to perform counting of the number of pulse outputs from the first light-receiving unit in the first to nth regions, and
• a comparator for results of the counting,
• the initial configuration circuit determines by the comparator, a region in which a counter value is largest among the first to nth regions,
• when the initial configuration circuit gives, as the initial phase value, the region determined to the first DLL circuit to cause the first DLL circuit to perform a converging operation, the initial configuration circuit outputs, as a phase configuration pulse signal, a signal cyclically achieving a High voltage in the region in which the counter value is largest to a pulse width increasing circuit, and
• the pulse width increasing circuit outputs a signal obtained by adding a prescribed width to a width of the phase configuration pulse signal to the first DLL circuit to cause the first DLL circuit to perform a converging operation to the region determined.