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US 2019/0195945 A1Published application
Tsv testing using test circuits and grounding means
AssigneeTexas Instruments Incorporated
InventorsLee D. Whetsel, Baher S. Haroun
Life of this patent
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Abstract
This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.
Claims10
A semiconductor apparatus comprising:
- (a) plural through silicon vias, each through silicon via having a first end and a second end;
- (b) plural test circuits, each test circuit is associated with a through silicon via and each test circuit includes:
- a sensed voltage input coupled to the first end of the associated through silicon via;
- a reference voltage input;
- a comparator having a first input coupled to the sensed voltage input, a second input coupled to the reference voltage input, and having a comparator output, the comparator generating a comparison signal by comparing voltage on the sensed voltage node and voltage on the reference voltage node;
- a scan cell having a scan input, a scan output, and a comparator input coupled to the comparator output, in which a stored comparison signal is operable to be shifted out from the scan output;
- and
- at least some of the plural test circuits are connected in series by connecting a scan output of one test circuit to a scan input of another test circuit.
5 more elements
A semiconductor device comprising:
- (a) a first through silicon via having a first end and a second end;
- (b) a first test circuit including:
- a first sensed voltage input coupled to the first end of the first through silicon via;
- a first reference voltage input;
- a first comparator having a first input coupled to the sensed voltage input, a second input coupled to the reference voltage input, and having a first comparator output;
- a first scan cell having a first scan input, a first scan output, and a first comparator input coupled to the first comparator output;
- (c) a second through silicon via separate from the first through silicon via, the second through silicon via having a first end and a second end;
- (d) a second test circuit including:
- a second sensed voltage input coupled to the first end of the second through silicon via;
- a second reference voltage input coupled to the first reference voltage input;
- a second comparator having a first input coupled to the second sensed voltage input, a second input coupled to the reference voltage input, and having a second comparator output;
- and
- a second scan cell having a second scan input, a second scan output, and a second comparator input coupled to the second comparator output, and the second scan output being coupled to the first scan input.
10 more elements
Dependencies are inferred from the claim text.