Ic degradation management circuit, system and method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPo-Zeng KANG, Chih-Hsien CHANG, Wen-Shen CHOU, Yung-Chow PENG
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Abstract
An IC degradation sensor is disclosed. The IC degradation management sensor includes an odd number of first logic gates electrically connected in a ring oscillator configuration, each first logic gate having an input and an output. Each first logic gate further includes a first PMOS transistor, a first NMOS transistor and a second logic gate having an input and an output. The input of the second logic gate is the input of the first logic gate, and the drains of the first PMOS transistor and the first NMOS transistor are electrically connected to the output of the second logic gate, and the output of the second logic gate is the output of the first logic gate.
Claims20
A method for degradation management, the method comprising:
- measuring a first instance of a stress parameter at a selected one of a plurality of dies;
- applying a stress mode setting to an IC degradation management sensor of the selected die for a first period of stress time;
- switching to a measurement mode setting on the IC degradation management sensor on the selected die after the first period of stress time;
- measuring a second instance of the stress parameter after the first period of stress time;
- and
- generating a predicted lifetime value for the selected die.
Dependencies are inferred from the claim text.